In testing a semiconductor memory for example, it is necessary to generate timing signals which have various phase (delay time) differences. Waveforms shown on device data sheets describe a complex interrelationship among input and address data, clock and control signals, and output data. These waveforms, usually with edges specified to within one nanosecond, must be accurately reproduced if a test system is to do its job. For example, an integrated circuit test system which contains a delay signal generating circuit of the present invention is able to generate input waveforms whose edges can be programmed in 100 picosecond steps over the range from 0 to 100 microseconds and to deliver them accurately to the pins of the memory under test. For generating these timing signals, a fixed period clock is provided to delay circuits whose delay time resolution is better than the clock period. Examples of such circuits are illustrated in FIGS. 1a and 1b.
In FIG. 1a, each reference clock pulse Pa is provided to each input of the variable delay circuit 2a, 2b, 2c, 2d, 2e, 2f from the pulse generator 1. Each delay circuit provides a delay pulse Pb to Pg as in FIG. 2, each of which is delayed by a respective predetermined time. Multiplexer 3 selects a desired signal from Pb to Pg and outputs the delayed signal Po at the output terminal 5.
In FIG. 1b, the variable delay circuits 2a to 2f are connected in series. Each delay circuit has in parallel a switch circuit to selectively add the respective delay time to the total delay time of the series connection. As mentioned above, the minimum delay time of these circuits is smaller than the time interval between the clock pulses Pa, to avoid the timing signal resolution becoming limited by the clock period or resolution.
Each variable delay circuit 2a to 2f may be constructed in a known manner as illustrated in FIG. 3. Here the delay time is varied by the voltage change at the input of the delay unit 7 caused by the potentiometer 3. The delay unit 7 is usually formed with a resistance and a variable capacitance diode, forming an RC network. The relay circuit 6 is connected between the input 4 and the output 5 via the OR circuit 19 to change from the delayed to the nondelayed state or vice versa.
In this known means for adjusting a delay time, it is necessary to adjust the potentiometer 3 manually to search for a suitable voltage for the delay unit 7. When adjusting the potentiometer 3, both the reference clock and the delayed pulse are displayed on an oscilloscope screen, and by observing the time difference between these two pulses, the desired delay time is adjusted by adjusting the potentiometer 3 to make the time difference a suitable amount.
Because the measurement and adjustment are made by use of an oscilloscope, the accuracy of the delay time depends on the accuracy of the oscilloscope. Also, error arising from reading the difference off the oscilloscope screen makes the accuracy even worse. Further, it is time consuming to adjust each delay circuit manually, because a typical integrated circuit test system contains many delay circuits of various form.